AVR instruction set

Instruction Set Nomenclature:

Status Register (SREG):
SREG: Status register
C: Carry flag in status register
Z: Zero flag in status register
N: Negative flag in status register
V: Twos complement overflow indicator
S: N V, For signed tests
H: Half Carry flag in the status register
T: Transfer bit used by BLD and BST instructions
I: Global interrupt enable/disable flag
X,Y,Z: Indirect address register (X=R27:R26,
Y=R29:R28 and Z=R31:R30)
P: I/O port address
q: Displacement for direct addressing (6 bit)

I/O Registers
RAMPX, RAMPY, RAMPZ: Registers concatenated with
the X, Y and Z registers enabling indirect addressing of the
whole SRAM area on MCUs with more than 64K bytes
SRAM.
Registers and operands:
Rd: Destination (and source) register in the register file
Rr: Source register in the register file
R: Result after instruction is executed
K: Constant literal or byte data (8 bit)
k: Constant address data for program counter
b: Bit in the register file or I/O register (3 bit)
s: Bit in the status register (3 bit)

Stack:
STACK:Stack for return address and pushed registers
SP: Stack Pointer to STACK

Flags:
: Flag affected by instruction
0: Flag cleared by instruction
1: Flag set by instruction
-: Flag not affected by instruction

ARITHMETIC AND LOGIC INSTRUCTIONS

MnemonicsOperandsDescriptionOperationFlagsClocks
ADDRd, RrAdd without CarryRdRd + RrZ,C,N,V,H1
ADCRd, RrAdd with CarryRdRd + Rr + CZ,C,N,V,H1
ADIWRd, KAdd Immediate to WordRd+1:RdRd+1:Rd + KZ,C,N,V2
SUBRd, RrSubtract without CarryRdRd - RrZ,C,N,V,H1
SUBIRd, KSubtract ImmediateRdRd - KZ,C,N,V,H1
SBCRd, RrSubtract with CarryRdRd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract Immediate with CarryRdRd - K - CZ,C,N,V,H1
SBIWRd, KSubtract Immediate from WordRd+1:RdRd+1:Rd - KZ,C,N,V2
ANDRd, RrLogical ANDRdRd RrZ,N,V1
ANDIRd, KLogical AND with ImmediateRdRd KZ,N,V1
ORRd, RrLogical ORRdRd v RrZ,N,V1
ORIRd, KLogical OR with ImmediateRd Rd v KZ,N,V1
EORRd, RrExclusive ORRdRdRrZ,N,V1
COMRdOne's ComplementRd$FF - RdZ,C,N,V1
NEGRdTwo's ComplementRd$00 - RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRdRd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRdRd ($FFh - K)Z,N,V1
INCRdIncrementRdRd + 1Z,N,V1
DECRdDecrementRdRd - 1Z,N,V1
TSTRdTest for Zero or MinusRdRd RdZ,N,V1
CLRRdClear RegisterRdRdRdZ,N,V1
SERRdSet RegisterRd$FFNone1
CPRd,RrCompareRd - RrZ,C,N,V,H1
CPCRd,RrCompare with CarryRd - Rr - CZ,C,N,V,H1
CPIRd,KCompare with ImmediateRd - KZ,C,N,V,H1

BRANCH INSTRUCTIONS

MnemonicsOperandsDescriptionOperationFlagsClocks
RJMPkRelative JumpPCPC + k + 1None2
IJMPIndirect Jump to (Z)PCZNone2
JMPkJumpPCkNone3
RCALLkRelative Call SubroutinePCPC + k + 1None3
ICALLIndirect Call to (Z)PCZNone3
CALLkCall SubroutinePCkNone4
RETSubroutine ReturnPCSTACKNone4
RETIInterrupt ReturnPCSTACKI4
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PCPC + 2 or 3None1 / 2 / 3
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PCPC + 2 or 3None1 / 2 / 3
SBRSRr, bSkip if Bit in Register Setif (Rr(b)=1) PCPC + 2 or 3None1 / 2 / 3
SBICP, bSkip if Bit in I/O Register Clearedif(I/O(P,b)=0) PCPC + 2 or 3None1 / 2 / 3
SBISP, bSkip if Bit in I/O Register SetIf(I/O(P,b)=1) PCPC + 2 or 3None1 / 2 / 3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PCPC+k + 1None1 / 2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PCPC+k + 1None1 / 2
BREQkBranch if Equalif (Z = 1) then PCPC + k + 1None1 / 2
BRNEkBranch if Not Equalif (Z = 0) then PCPC + k + 1None1 / 2
BRCSkBranch if Carry Setif (C = 1) then PCPC + k + 1None1 / 2
BRCCkBranch if Carry Clearedif (C = 0) then PCPC + k + 1None1 / 2
BRSHkBranch if Same or Higherif (C = 0) then PC PC + k + 1None1 / 2
BRLOkBranch if Lowerif (C = 1) then PCPC + k + 1None1 / 2
BRMIkBranch if Minusif (N = 1) then PCPC + k + 1None1 / 2
BRPLkBranch if Plusif (N = 0) then PCPC + k + 1None1 / 2
BRGEkBranch if Greater or Equal, Signedif (NV= 0) then PCPC+ k + 1None1 / 2
BRLTkBranch if Less Than, Signedif (NV= 1) then PCPC + k + 1None1 / 2
BRHSkBranch if Half Carry Flag Setif (H = 1) then PCPC + k + 1None1 / 2
BRHCkBranch if Half Carry Flag Clearedif (H = 0) then PCPC + k + 1None1 / 2
BRTSkBranch if T Flag Setif (T = 1) then PCPC + k + 1None1 / 2
BRTCkBranch if T Flag Clearedif (T = 0) then PCPC + k + 1None1 / 2
BRVSkBranch if Overflow Flag is Setif (V = 1) then PCPC + k + 1None1 / 2
BRVCkBranch if Overflow Flag is Clearedif (V = 0) then PCPC + k + 1None1 / 2
BRIEkBranch if Interrupt Enabledif ( I = 1) then PCPC + k + 1None1 / 2
BRIDkBranch if Interrupt Disabledif ( I = 0) then PCPC + k + 1None1 / 2

DATA TRANSFER INSTRUCTIONS

MnemonicsOperandsDescriptionOperationFlagsClocks
MOVRd, RrCopy RegisterRdRrNone1
LDIRd, KLoad ImmediateRdKNone1
LDSRd, kLoad Direct from SRAMRd(k)None3
LDRd, XLoad IndirectRd(X)None2
LDRd, X+Load Indirect and Post-IncrementRd(X), XX + 1None2
LDRd, -XLoad Indirect and Pre-DecrementXX - 1, Rd (X)None2
LDRd, YLoad IndirectRd(Y)None2
LDRd, Y+Load Indirect and Post-IncrementRd(Y), YY + 1None2
LDRd, -YLoad Indirect and Pre-DecrementYY - 1, Rd(Y)None2
LDDRd,Y+qLoad Indirect with DisplacementRd(Y + q)None2
LDRd, ZLoad IndirectRd(Z)None2
LDRd, Z+Load Indirect and Post-IncrementRd(Z), ZZ+1None2
LDRd, -ZLoad Indirect and Pre-DecrementZZ - 1, Rd(Z)None2
LDDRd, Z+qLoad Indirect with DisplacementRd(Z + q)None2
STSk, RrStore Direct to SRAMRd(k)None3
STX, RrStore Indirect(X)RrNone2
STX+, RrStore Indirect and Post-Increment(X)Rr, XX + 1None2
ST-X, RrStore Indirect and Pre-DecrementXX - 1, (X) RrNone2
STY, RrStore Indirect(Y)RrNone2
STY+, RrStore Indirect and Post-Increment(Y)Rr, YY + 1None2
ST-Y, RrStore Indirect and Pre-DecrementYY - 1, (Y)RrNone2
STDY+q,RrStore Indirect with Displacement(Y + q)RrNone2
STZ, RrStore Indirect(Z)RrNone2
STZ+, RrStore Indirect and Post-Increment(Z)Rr, ZZ + 1None2
ST-Z, RrStore Indirect and Pre-DecrementZZ - 1, (Z)RrNone2
STDZ+q,RrStore Indirect with Displacement(Z + q)RrNone2
LPMLoad Program MemoryR0(Z)None3
INRd, PIn PortRdPNone1
OUTP, RrOut PortPRrNone1
PUSHRrPush Register on StackSTACKRrNone2
POPRdPop Register from StackRdSTACKNone2

BIT AND BIT-TEST INSTRUCTIONS

MnemonicsOperandsDescriptionOperationFlags#Clock Note
LSLRdLogical Shift LeftRd(n+1)Rd(n),Rd(0)0,CRd(7)Z,C,N,V,H1
LSRRdLogical Shift RightRd(n)Rd(n+1),Rd(7)0,CRd(0)Z,C,N,V1
ROLRdRotate Left Through CarryRd(0)C,Rd(n+1)Rd(n),CRd(7)Z,C,N,V,H1
RORRdRotate Right Through CarryRd(7)C,Rd(n)Rd(n+1),CRd(0)Z,C,N,V1
ASRRdArithmetic Shift RightRd(n)Rd(n+1), n=0..6Z,C,N,V1
SWAPRdSwap NibblesRd(3..0)Rd(7..4)None1
BSETsFlag SetSREG(s)1SREG(s)1
BCLRsFlag ClearSREG(s)0SREG(s)1
SBIP, bSet Bit in I/O RegisterI/O(P, b)1None2
CBIP, bClear Bit in I/O RegisterI/O(P, b)0None2
BSTRr, bBit Store from Register to TTRr(b)T1
BLDRd, bBit load from T to RegisterRd(b)TNone1
SECSet CarryC1C1
CLCClear CarryC0C1
SENSet Negative FlagN1N1
CLNClear Negative FlagN0N1
SEZSet Zero FlagZ1Z1
CLZClear Zero FlagZ0Z1
SEIGlobal Interrupt EnableI1I1
CLIGlobal Interrupt DisableI0I1
SESSet Signed Test FlagS1S1
CLSClear Signed Test FlagS0S1
SEVSet Two's Complement OverflowV1V1
CLVClear Two's Complement OverflowV0V1
SETSet T in SREGT1T1
CLTClear T in SREGT0T1
SEHSet Half Carry Flag in SREGH1H1
CLHClear Half Carry Flag in SREGH0H1
NOPNo OperationNone1
SLEEPSleep(see specific descr. for Sleep)None1
WDRWatchdogReset (see specific descr. for WDR)None1