Crystals

• Too SMALL a feedback resistance, and you have insufficent Phase Margin to OSC



• Too SMALL a Capacitance, and the same effect occurs



• Too LARGE a Capacitance, and the gain falls below that needed for Osc



• Nett Parallel C across the XTAL determines Freq, but it does not have to be split 50/50%



• The CAP neeeded for a given phase shift, when driven by the amplifier Zo will INCREASE as the freq reduces. The Zo depends very much on the Chip design and is the likely culprit for these 'chip revision' stories that do the rounds..



• You can get a 3rd overtone XTAL, to run, with a relatively LOW parallel R ( 6K8) and a small input C. This provides insufficent Phase shift on fundamental, but still has enough gain to OSC at the overtone.
  Bring the supply up very slowly, and you can see the XTAL go indecisive - Fund or 3rd ?



• All XTALS, resonators, and even LC circuits have a finite Startup time, literally for the vibration to build up. It is inversely proportional to Q, and depends also on the phase margin



• On a C51 ( & AVR ? ), the internal Osc buffer ( not the osc inverter ) is fed from XTAL1 and is a Schmitt trigger - so, amplitude on the XTAL IN pin matters, not that on XTAL out.
  The Schmitt provides a simple way to ensure a certain amplitude is needed before clocking starts ( as well as giving fast edges )



• You CAN have a circuit oscillate, but with low amplitude on XTAL1, and then not reliably trigger the schmitt, for core clocking.
  Also, on a AVR, the DUTY cycle HI:LO will be more critical than a C51, as the C51 uses a Divide by 2 FlipFlop straight after the Xtal Buffer



• XTAL Oscs will start at quite low voltages ( < 2V ), and it is possible to overclock the core at these voltages - ie the OSC is too fast, and the core gets lost - so a RESET should be provided that is long enough for Osc StartUp, and also long enough for the Core to get to > Min Voltage, at which it can cope with the XTAL freq.


Power the whole circuit off a ~30Hz sq wave, and watch the OSC startups.