The 555 timer is shown connected as a monostable timer.

The potential divider R1, R2, R3 provides 1/3 Vcc at the non inverting input of the lower comparator.
It also provides 2/3 Vcc at the inverting input of the upper comparator.

The comparator outputs control the inputs of the SR flip-flop which in turn controls the output stage and TR1.
The flip-flop can also be controlled by the Reset input.

In the stable state pin 2 is held high by R4.
The output of the lower comparator is low, the output of the flip-flop is high.
Tr1 is on,C1 is discharged and output at pin 3 is low.
 

The monostable is initiated by a negative going pulse to pin 2.

When this pulse falls below 1/3 Vcc the lower comparator makes S high and the output of the flip-flop goes low.
This turns off TR1 allowing C to charge. Pin 3 goes high.

The capacitor charges via Rt until the voltage rises to 2/3 Vcc, at which point the upper comparator changes state.
This resets the flip-flop, its output going high which turns on TR1, discharging Ct.
The output at 3 goes low.
The timer has returned to its stable state.

Once triggered, the timer cannot be triggered again until the sequence is complete.
The sequence can be aborted by a negative pulse to "reset".
Timing periods can be varied by a variable resistance or voltage between pin 5 and ground.